A fast power current analysis methodology using capacitor charging model for side channel attack evaluation

Fast power current analysis method using capacitor charging model was introduced to evaluate security of cryptographic hardware against side channel attacks before the circuit is fabricated as an LSI chip. The method was applied to CPA (Correlation Power Analysis) on various AES (Advanced Encryption Standard) circuits, which require more than 10,000 power current traces, and simulation speed was accelerated by 40–60 times in comparison with conventional full transistor level analysis. The proposed simulation based CPA revealed all of the secret keys of the AES circuits by extracting capacitance model from the post-layout data using a 65-nm CMOS standard cell library. The layout was also fabricated as an LSI chip, and CPA on the LSI was conducted. The results showed remarkable consistency between simulation and actual measurement in terms of information leakage related to the secret keys in power waveforms.

[1]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[2]  Christophe Clavier,et al.  Correlation Power Analysis with a Leakage Model , 2004, CHES.

[3]  Takashi Morie,et al.  Physical design guides for substrate noise reduction in CMOS digital circuits , 2001 .

[4]  A. Satoh,et al.  Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing , 2011 .

[5]  Hugo De Man,et al.  SWAN: high-level simulation methodology for digital substrate noise generation , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  S. Yang,et al.  AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks , 2006, IEEE Journal of Solid-State Circuits.

[7]  Kenji Shimazaki,et al.  A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[8]  Thomas Popp,et al.  Evaluation of Power Estimation Methods Based on Logic Simulations , 2007 .

[9]  Stéphane Badel,et al.  A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies , 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

[10]  Makoto Nagata,et al.  Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits , 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..