Circuit and architecture trade-offs for high-speed multiplication

VLSI implementations of high-performance parallel multipliers are discussed. Circuit building blocks required for partial-product reduction are analyzed and two schemes leading to highly regular layouts are proposed. The circuit implementations related to the first-scheme in three different BiCMOS technologies are discussed. The die size and performance for nominal design rule values are compared, and the trend in scaling the feature sizes is studied. A silicon implementation of a prototype slice of an IEEE double-precision floating point multiplier in a 0.8- mu m double-metal BiCMOS technology is presented. >

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