Techniques to speedup test generation for vlsi circuits

The increasing complexity of logic circuits has made the problem of test generation intractable. In this dissertation we investigate three different techniques to speed up the test generation process. The first approach attempts to exploit the hierarchy inherent in any complex digital design. An intermediate high-level representation is proposed, and algorithms to perform forward implication and backtracing in the proposed framework are developed. Results of test generation experiments based on this approach are also presented. The second technique deals with the use of heuristics in test generation algorithms. Based on an extensive study of five existing testability measures, a composite test generation strategy is evaluated. The composite strategy uses multiple testability measures to aid the test generation guidance heuristic. Our results indicate that this strategy not only gives better fault coverage but also reduces the average time taken per fault. Finally we investigate the viability of parallel processing for test generation. Schemes for mapping test generation algorithms onto different classes of parallel machines are presented. The performance of these mapping strategies is predicted based on uniprocessor turnaround times and an estimate of the communication delays.