How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the ICs are in the normal operating condition. A cascode design is therefore proposed to safely apply the low voltage triggered SCR (LVTSCR) devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latch-up danger. Such cascoded LVTSCRs with a holding voltage greater than V/sub DD/ of an IC can provide CMOS ICs with effective component-level ESD protection but without being accidentally triggered by system-level overshooting or undershooting noise pulses.

[1]  Chung-Yu Wu,et al.  Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[2]  Chung-Yu Wu,et al.  Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI , 1996 .

[3]  R. N. Rountree.  ESD protection for submicron CMOS circuits-issues and solutions , 1988, Technical Digest., International Electron Devices Meeting.

[4]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[5]  G.H. Weiss,et al.  Transient-induced latchup testing of CMOS integrated circuits , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[6]  Ming-Dou Ker.  ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current , 1997 .

[7]  Guido Notermans,et al.  Using an SCR as ESD protection without latch-up danger , 1997 .

[8]  Chung-Yu Wu,et al.  Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's , 1995 .

[9]  J.Y. Chen,et al.  Latchup performance of retrograde and conventional n-well CMOS technologies , 1987, IEEE Transactions on Electron Devices.

[10]  Chung-Yu Wu,et al.  A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI , 1992 .

[11]  Ming-Dou Ker.  Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology , 1998 .

[12]  Gregg D. Croft.  ESD protection using a variable voltage supply clamp , 1995 .

[13]  Carlos H. Díaz,et al.  Bi-modal triggering for LVSCR ESD protection devices☆ , 1995 .

[14]  Bernard G. Carbajal,et al.  A successful HBM ESD protection circuit for micron and sub-micron level CMOS , 1993 .

[15]  Chung-Yu Wu,et al.  ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure , 1995, Proceedings of International Electron Devices Meeting.

[16]  Wolfgang Nikutta,et al.  Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress (MOS devices) , 1993 .

[17]  R.A. Martin,et al.  A new process for one micron and finer CMOS , 1985, 1985 International Electron Devices Meeting.

[18]  Chung-Yu Wu,et al.  A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs , 1997 .

[19]  Ming-Dou Ker,et al.  Whole-chip ESD protection design for submicron CMOS VLSI , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[20]  Anh Bui,et al.  Unique ESD failure mechanisms during negative to Vcc HBM tests , 1998 .

[21]  Chung-Yu Wu,et al.  CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage , 1994 .

[22]  Ming-Dou Ker.  ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices , 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

[23]  Charvaka Duvvury,et al.  A synthesis of ESD input protection scheme , 1992 .

[24]  Ming-Dou Ker,et al.  Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC , 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.

[25]  A. J. Walker,et al.  A hot-carrier triggered SCR for smart power bus ESD protection , 1995, Proceedings of International Electron Devices Meeting.

[26]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[27]  T. Polgreen,et al.  A low-voltage triggering SCR for on-chip ESD protection at output and input pads , 1990, IEEE Electron Device Letters.

[28]  Chung-Yu Wu,et al.  Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.