Symbolic Trajectory Evaluation

data types can be declared in FL. This means that data can be represented and manipulated at a high level. This is important for making specifications understandable, and critical for overcoming the limitations of BDDs. FL provides built-in functions that are the interface to the STE engine. The use of a fully programmable script language is a key factor in implementing our verification methodology. It means that our tool can be simple, but through the use of a flexible interface, a user can verify a wide range of problems. On top of Voss’s facilities, we have implemented a simple theorem prover to implement the compositional theory presented in Section 5.3 – we have called this augmented system called VossProver. We have actually implemented a number of such tools, experimenting with style and functionality. The description presented here is a general description of one of the latest versions.

[1]  Jeffrey J. Joyce,et al.  Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving , 1993, 30th ACM/IEEE Design Automation Conference.

[2]  E.M. Clarke,et al.  Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[3]  Mark Ryan,et al.  Valuation systems and consequence relations , 1993, LICS 1993.

[4]  Teuvo Kohonen,et al.  Associative memory. A system-theoretical approach , 1977 .

[5]  Somesh Jha,et al.  Exploiting symmetry in temporal logic model checking , 1993, Formal Methods Syst. Des..

[6]  Randal E. Bryant,et al.  Formal Verification of Digital Circuits Using Symbolic Ternary System Models , 1990, CAV.

[7]  Edmund M. Clarke,et al.  Model checking, abstraction, and compositional verification , 1993 .

[8]  Randal E. Bryant,et al.  Formal hardware verification by symbolic ternary trajectory evaluation , 1991, 28th ACM/IEEE Design Automation Conference.

[9]  Claire Loiseaux,et al.  A Tool for Symbolic Program Verification and Abstration , 1993, CAV.

[10]  Edmund M. Clarke,et al.  Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Randal E. Bryant,et al.  Symbolic Verification of MOS Circuits , 1985 .

[12]  Edmund M. Clarke,et al.  Model checking and abstraction , 1994, TOPL.

[13]  Melvin Fitting,et al.  Bilattices and the theory of truth , 1989, J. Philos. Log..

[14]  Carl-Johan H. Seger,et al.  A simple theorem prover based on symbolic trajectory evaluation and BDD's , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Eugene D. Fabricius,et al.  Introduction to VLSI design , 1990, McGraw-Hill series in electrical engineering.

[16]  Ganesh Gopalakrishnan,et al.  Efficient symbolic simulation-based verification using the parametric form of Boolean expressions , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Randal E. Bryant,et al.  A methodology for hardware verification based on logic simulation , 1987, JACM.

[18]  Albert Visser,et al.  Four valued semantics and the Liar , 1984, J. Philos. Log..

[19]  Carl-Johan H. Seger,et al.  The formal verification of a pipelined double-precision IEEE floating-point multiplier , 1995, ICCAD.

[20]  Zheng Zhu,et al.  The Completeness of a Hardware Inference System , 1994, CAV.

[21]  J. Davenport Editor , 1960 .

[22]  D. Beatty A methodology for formal hardware verification, with application to microprocessors , 1993 .

[23]  David L. Dill,et al.  Automatic verification of Pipelined Microprocessor Control , 1994, CAV.

[24]  Nuel D. Belnap,et al.  A Useful Four-Valued Logic , 1977 .

[25]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[26]  Randal E. Bryant,et al.  On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.

[27]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[28]  Randal E. Bryant,et al.  Formal verification by symbolic evaluation of partially-ordered trajectories , 1995, Formal Methods Syst. Des..

[29]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[30]  Pierre Wolper,et al.  Symbolic Verification with Periodic Sets , 1994, CAV.

[31]  Daniel Brand,et al.  Symbolic Simulation for Correct Machine Design , 1979, 16th Design Automation Conference.

[32]  Dov M. Gabbay,et al.  Background : computational structures , 1992 .

[33]  Melvin Fitting,et al.  Bilattices and the Semantics of Logic Programming , 1991, J. Log. Program..

[34]  S. Hazelhurst,et al.  Compositional Model Checking of Partially Ordered State Spaces , 1996 .

[35]  Luc J. M. Claesen,et al.  Formal VLSI correctness verification : proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design , 1990 .

[36]  G. Winskel,et al.  A Compositional Proof System for the Modal mu-Calculus , 1994 .

[37]  Mohammad Mostafa Darwish Formal verification of a 32-bit pipelined RISC processor , 1994 .

[38]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[39]  R. Bryant,et al.  Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .

[40]  Steven D. Johnson,et al.  Studies of the Single Pulser in Various Reasoning Systems , 1994, TPCD.

[41]  Carl Seger VOSS - A Formal Hardware Verification System User''s Guide , 1993 .

[42]  Costas Courcoubetis Proceedings of the 5th International Conference on Computer Aided Verification , 1993 .

[43]  Martín Abadi,et al.  Conjoining specifications , 1995, TOPL.

[44]  Orna Grumberg,et al.  Model checking and modular verification , 1994, TOPL.

[45]  H. Piaggio Mathematical Analysis , 1955, Nature.

[46]  Xudong Zhao,et al.  Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits , 1995 .

[47]  J. V. Tucker,et al.  Algebraic Models and the Correctness of Microprocessors , 1993, CHARME.