论文信息 - Analysis and control of hysteresis in PD/SOI CMOS

Analysis and control of hysteresis in PD/SOI CMOS

A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100 nm.

J.G. Fossum | G.O. Workman | M.M. Pelella | M.-H. Chiang | C.R. Tretz

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