Evidence of Pulse Quenching in AND and OR Gates by Experimental Probing of Full Single-Event Transient Waveforms

We present experimental results obtained from full-waveform measurements of single-event transients (SETs) occurring in the conventional two-input AND and OR gates under focused heavy-ion radiation. Chips with test circuits were fabricated in a 65-nm bulk CMOS technology, and were irradiated in a microbeam facility using 197Au and 48Ca species. The resulting SETs were sensed using a dedicated on-chip analog multiplexer circuit. The obtained position-dependent ion hit responses were analyzed, and the strong evidence of charge-sharing-induced pulse quenching was observed. For SETs that propagated through the inverting stage of AND and OR circuits, a significant degradation of measured SET pulse widths and heights was seen. These observations are in good accordance with earlier published simulation and experimental results based on inverter chains. Test circuits also exhibited distinct SET responses depending on their logic state, making the AND gate a better candidate for exploiting the pulse quenching effect when circuits are placed in a triple well.

[1]  K. Avery,et al.  Single event transient pulsewidth measurements using a variable temporal latch technique , 2004, IEEE Transactions on Nuclear Science.

[2]  B.L. Bhuva,et al.  Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[3]  P.H. Eaton,et al.  Digital Single Event Transient Trends With Technology Node Scaling , 2006, IEEE Transactions on Nuclear Science.

[4]  B. Narasimham,et al.  On-Chip Characterization of Single-Event Transient Pulsewidths , 2006, IEEE Transactions on Device and Materials Reliability.

[5]  A.F. Witulski,et al.  Single Event Upsets in a 130 nm Hardened Latch Design Due to Charge Sharing , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[6]  B. Narasimham,et al.  Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.

[7]  peixiong zhao,et al.  Single Event Mechanisms in 90 nm Triple-Well CMOS Devices , 2008, IEEE Transactions on Nuclear Science.

[8]  P. Eaton,et al.  Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits , 2009, IEEE Transactions on Nuclear Science.

[9]  B L Bhuva,et al.  The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process , 2010, IEEE Transactions on Nuclear Science.

[10]  R. Allmon,et al.  On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  Masanori Hashimoto,et al.  Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[12]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[13]  W. T. Holman,et al.  Layout Technique for Single-Event Transient Mitigation via Pulse Quenching , 2011, IEEE Transactions on Nuclear Science.

[14]  L. W. Massengill,et al.  Effect of Multiple-Transistor Charge Collection on Single-Event Transient Pulse Widths , 2011, IEEE Transactions on Device and Materials Reliability.

[15]  J. Segura,et al.  Analytical Modeling of Single Event Transients Propagation in Combinational Logic Gates , 2012, IEEE Transactions on Nuclear Science.

[16]  A. Steininger,et al.  Pulse Shape Measurements by On-Chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain , 2012, IEEE Transactions on Nuclear Science.

[17]  Chen Shuming,et al.  Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology , 2012, IEEE Transactions on Nuclear Science.

[18]  T. D. Loveless,et al.  Angled flip-flop single-event cross sections for submicron bulk CMOS technologies , 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

[19]  Horst Zimmermann,et al.  A DC-to-8.5 GHz 32 : 1 Analog Multiplexer for On-Chip Continuous-Time Probing of Single-Event Transients in a 65-nm CMOS , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[20]  Horst Zimmermann,et al.  Experimental Investigation of Single-Event Transient Waveforms Depending on Transistor Spacing and Charge Sharing in 65-nm CMOS , 2017, IEEE Transactions on Nuclear Science.