Hammer: a modular and reusable physical design flow tool: invited

Process technology scaling and hardware architecture specialization have vastly increased the need for chip design space exploration, while optimizing for power, performance, and area. Hammer is an open-source, reusable physical design (PD) flow generator that reduces design effort and increases portability by enforcing a separation among design-, tool-, and process technology-specific concerns with a modular software architecture. In this work, we outline Hammer's structure and highlight recent extensions that support both physical chip designers and hardware architects evaluating the merit and feasibility of their proposed designs. This is accomplished through the integration of more tools and process technologies---some open-source---and the designer-driven development of flow step generators. An evaluation of chip designs in process technologies ranging from 130nm down to 12nm across a series of RISC-V-based chips shows how Hammer-generated flows are reusable and enable efficient optimization for diverse applications.

[1]  Christopher Torng,et al.  Enabling Reusable Physical Design Flows with Modular Flow Generators , 2021, ArXiv.

[2]  Jan M. Rabaey,et al.  A Highly Energy-Efficient Hyperdimensional Computing Processor for Wearable Multi-Modal Classification , 2021, 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[3]  Jerry Zhao,et al.  A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET , 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

[4]  Jan M. Rabaey,et al.  Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata , 2021, Brain Informatics.

[5]  Mohamed Shalan,et al.  Real Silicon Using Open-Source EDA , 2021, IEEE Design & Test.

[6]  Mohamed Shalan,et al.  Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[7]  Krste Asanovic,et al.  Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs , 2020, IEEE Micro.

[8]  Elad Alon,et al.  A Methodology for Reusable Physical Design , 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

[9]  Albert J. Ou,et al.  Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures , 2019, ArXiv.

[10]  Andrew B. Kahng,et al.  INVITED: Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[11]  Adam M. Izraelevitz Unlocking Design Reuse with Hardware Compiler Frameworks , 2019 .

[12]  David Renshaw,et al.  European Solid-State Circuits Conference (ESSCIRC) , 1987 .