3-D TSV Six-Die Stacking and Reliability Assessment of 20- $\mu$ m-Pitch Bumps on Large-Scale Dies
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[1] Daniel Rhee Min Woo,et al. Process development of multi-die stacking using 20 um pitch micro bumps on large scale dies , 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
[2] Da-Yuan Shih,et al. Ag3Sn plate formation in the solidification of near-ternary eutectic Sn-Ag-Cu , 2003 .
[3] Vempati Srinivasa Rao,et al. Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer , 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
[4] R. Beica,et al. Advanced Metallization for 3D Integration , 2008, 2008 10th Electronics Packaging Technology Conference.
[5] Luca Benini,et al. Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.
[6] H. Tu,et al. Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[7] K. Soejima,et al. A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.
[8] Srinivasa Rao Vempati,et al. Chip to wafer bonding for three-dimensional integration of copper low K Chip by stacking process , 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
[9] S. Pamarthy,et al. Process Integration Considerations for 300 mm TSV Manufacturing , 2009, IEEE Transactions on Device and Materials Reliability.
[10] C.H. Chang,et al. High density 3D integration using CMOS foundry technologies for 28 nm node and beyond , 2010, 2010 International Electron Devices Meeting.