Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.

[1]  A. S. Grove,et al.  Characteristics of the Surface‐State Charge (Qss) of Thermally Oxidized Silicon , 1967 .

[2]  J. F. Verwey,et al.  Nonvolatile Semiconductor Memories , 1976 .

[3]  K. Jeppson,et al.  Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices , 1977 .

[4]  James D. Plummer,et al.  Si‐SiO2 interface trap production by low‐temperature thermal processing , 1987 .

[5]  M. L. Reed,et al.  Chemistry of Si‐SiO2 interface trap annealing , 1988 .

[6]  E. H. Nicollian,et al.  Mechanism of negative‐bias‐temperature instability , 1991 .

[7]  Chenming Hu.  Nonvolatile semiconductor memories : technologies, design, and applications , 1991 .

[8]  T. Yamamoto,et al.  A new degradation mode of scaled p/sup +/ polysilicon gate pMOSFETs induced by bias temperature (BT) instability , 1995, Proceedings of International Electron Devices Meeting.

[9]  E. Cartier,et al.  MECHANISM FOR STRESS-INDUCED LEAKAGE CURRENTS IN THIN SILICON DIOXIDE FILMS , 1995 .

[10]  Ogawa,et al.  Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. , 1995, Physical review. B, Condensed matter.

[11]  E. Crabbé,et al.  NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[12]  G. V. Gadiyak.  Hydrogen redistribution in thin silicon dioxide films under electron injection in high fields , 1997 .

[13]  P.J. Silverman,et al.  Explanation of stress-induced damage in thin oxides , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[14]  K. Yamaguchi,et al.  The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[15]  T. Mogami,et al.  Bias temperature instability in scaled p/sup +/ polysilicon gate p-MOSFET's , 1999 .

[16]  Shinichi Takagi,et al.  Experimental evidence of inelastic tunneling in stress-induced leakage current , 1999 .

[17]  T. Kubota,et al.  Bias-temperature degradation of pMOSFETs: mechanism and suppression , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[18]  J. McPherson,et al.  Complementary model for intrinsic time-dependent dielectric breakdown in SiO2 dielectrics , 2000 .

[19]  P. Chaparala,et al.  Threshold voltage drift in PMOSFETS due to NBTI and HCI , 2000, 2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515).

[20]  A. Ghetti,et al.  Field acceleration for oxide breakdown-can an accurate anode hole injection model resolve the E vs. 1/E controversy? , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[21]  M. Alam,et al.  The prospect of using thin oxides for silicon nanotransistors , 2001, Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 (IEEE Cat. No.01EX537).

[22]  Muhammad A. Alam,et al.  SILC as a measure of trap generation and predictor of T/sub BD/ in ultrathin oxides , 2002 .

[23]  A. Toriumi,et al.  NBTI mechanism in ultra-thin gate dielectric - nitrogen-originated mechanism in SiON , 2002, Digest. International Electron Devices Meeting,.

[24]  Muhammad Ashraful Alam.  SILC as a Measure of Trap Generation and Predictor of in Ultrathin Oxides , 2002 .

[25]  S. Mahapatra,et al.  A predictive reliability model for PMOS bias temperature degradation , 2002, Digest. International Electron Devices Meeting,.

[26]  D. Kwong,et al.  Dynamic NBTI of PMOS transistors and its impact on device lifetime , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[27]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[28]  N. Mielke,et al.  Universal recovery behavior of negative bias temperature instability [PMOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[29]  S. Mahapatra,et al.  A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[30]  F. Monsieur,et al.  Evidence for hydrogen-related defects during NBTl stress in p-MOSFETs , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[31]  Chris G. Van de Walle,et al.  Universal alignment of hydrogen levels in semiconductors, insulators and solutions , 2003, Nature.

[32]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[33]  M.A. Alam,et al.  A critical examination of the mechanics of dynamic NBTI for PMOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[34]  R. Tsuchiya,et al.  Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[35]  J. Yugami,et al.  Two concerns about NBTI issue: gate dielectric scaling and increasing gate current , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[36]  V. Reddy,et al.  A comprehensive framework for predictive modeling of negative bias temperature instability , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.