Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators

Threshold implementations have emerged as one of the most popular masking countermeasures for hardware implementations of cryptographic primitives. In this work, we first provide a generic construction for \(d+1\) TI sharing which achieves the minimal number of output shares for any n-input Boolean function of degree \(t=n-1\) and for any d. Secondly, we demonstrate the applicability of our results on a first-order and second-order \(d+1\) low-latency PRINCE implementation.

[1]  Takafumi Aoki,et al.  A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares , 2017, 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL).

[2]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[3]  Anne Canteaut,et al.  PRINCE - A Low-Latency Block Cipher for Pervasive Computing Applications - Extended Abstract , 2012, ASIACRYPT.

[4]  Ingrid Verbauwhede,et al.  Consolidating Masking Schemes , 2015, CRYPTO.

[5]  Vincent Rijmen,et al.  Higher-Order Threshold Implementations , 2014, ASIACRYPT.

[6]  Stefan Mangard,et al.  Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order , 2016, IACR Cryptol. ePrint Arch..

[7]  Ingrid Verbauwhede,et al.  Fast Leakage Assessment , 2017, CHES.

[8]  Vincent Rijmen,et al.  Threshold Implementations of all 3x3 and 4x4 S-boxes , 2012, IACR Cryptol. ePrint Arch..

[9]  Yuval Ishai,et al.  Private Circuits: Securing Hardware against Probing Attacks , 2003, CRYPTO.

[10]  Stefan Mangard,et al.  Reconciling d+1 Masking in Hardware and Software , 2017, CHES.

[11]  Amir Moradi,et al.  Side-Channel Resistant Crypto for Less than 2,300 GE , 2011, Journal of Cryptology.

[12]  Roderick Bloem,et al.  Generic Low-Latency Masking in Hardware , 2018, IACR Trans. Cryptogr. Hardw. Embed. Syst..

[13]  Vincent Rijmen,et al.  Threshold Implementations Against Side-Channel Attacks and Glitches , 2006, ICICS.

[14]  Ventzislav Nikov,et al.  Low-Latency Encryption - Is "Lightweight = Light + Wait"? , 2012, CHES.

[15]  Amir Moradi,et al.  Side-Channel Analysis Protection and Low-Latency in Action - - Case Study of PRINCE and Midori - , 2016, ASIACRYPT.

[16]  Takafumi Aoki,et al.  Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation , 2017, COSADE.

[17]  Kyoji Shibutani,et al.  Midori: A Block Cipher for Low Energy , 2015, ASIACRYPT.