论文信息 - A CMOS sample and hold for high-speed ADCs

A CMOS sample and hold for high-speed ADCs

This paper presents an improved topology for a sample and hold (S/H) for high-speed ADCs. A S/H circuit designed following the described technique is also presented. Simulation results, referred to a 1.2 /spl mu/m CMOS technology, showed 10 bit resolution at 50 MHz sampling rate is achieved.

Guido Torelli | S. Brigati | Franco Maloberti

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