The impact of Miller and coupling effects on single event transient in logical circuits

With feature size scaling down, Miller feedback effects of gate-to-drain capacitance for transistors and coupling effects between interconnects will dramatically affect single event transient (SET) generation and propagation in combinational logic circuits. Two ways of ICs are arranged: linear and ''S'' types. For pulse width and delay time, SET propagations in two layouts of digital circuits are compared under considering the coupling effects between interconnects. An analytical model is used to describe the impact of Miller and coupling effects on SET propagation. A criterion for SET occurrence in digital circuits with effects of coupling and Miller feedback is presented. The influence of temperature and technology node on SET generation and propagation is analyzed. The results indicate that (1) the existence of these effects will improve the critical charge for SET generation and also reduce the estimated SER, and (2) the way of ''S'' type is more immune to SET than the scheme of linear.

[1]  Farshad Firouzi,et al.  An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects , 2011, Microelectron. Reliab..

[2]  Denis Flandre,et al.  Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs , 2010, Microelectron. Reliab..

[3]  M. L. Alles,et al.  Radiation effects in new materials for nano-devices , 2011 .

[4]  Chih-Peng Fan,et al.  Efficient RC low-power bus encoding methods for crosstalk reduction , 2011, Integr..

[5]  Zhi Yang,et al.  Interconnect crosstalk noise evaluation in deep-submicron technologies , 2009, Microelectron. Reliab..

[6]  Fernanda Gusmão de Lima Kastensmidt,et al.  Modeling the sensitivity of CMOS circuits to radiation induced single event transients , 2008, Microelectron. Reliab..

[7]  P.H. Eaton,et al.  Digital Single Event Transient Trends With Technology Node Scaling , 2006, IEEE Transactions on Nuclear Science.

[8]  Ming Zhang,et al.  Logic soft errors in sub-65nm technologies design and CAD challenges , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[9]  Mehdi Baradaran Tahoori,et al.  Soft error modeling and remediation techniques in ASIC designs , 2010, Microelectron. J..

[10]  Wang Yu,et al.  Soft error generation analysis in combinational logic circuits , 2010 .

[11]  F. Wrobel,et al.  Criterion for SEU occurrence in SRAM deduced from circuit and device Simulations in case of neutron-induced SER , 2005, IEEE Transactions on Nuclear Science.

[12]  Selahattin Sayil,et al.  Single Event crosstalk shielding for CMOS logic , 2009, Microelectron. J..

[13]  B. Narasimham,et al.  The Effect of Negative Feedback on Single Event Transient Propagation in Digital Circuits , 2006, IEEE Transactions on Nuclear Science.