Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing

We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.

[1]  W. Riess,et al.  Outperforming the Conventional Scaling Rules in the Quantum-Capacitance Limit , 2008, IEEE Electron Device Letters.

[2]  R. Chau.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004 .

[3]  David L. Pulfrey,et al.  Quantum capacitance in nanoscale device modeling , 2004 .

[4]  Costas P. Grigoropoulos,et al.  Non-melt laser annealing of Plasma Implanted Boron for ultra shallow junctions in Silicon , 2008 .

[5]  J. Knoch,et al.  Modeling of High-Performance p-Type III–V Heterojunction Tunnel FETs , 2010, IEEE Electron Device Letters.

[6]  G. Klimeck,et al.  Atomistic Full-Band Design Study of InAs Band-to-Band Tunneling Field-Effect Transistors , 2009, IEEE Electron Device Letters.

[7]  Yossi Rosenwaks,et al.  Measurement of active dopant distribution and diffusion in individual silicon nanowires. , 2010, Nano letters.

[8]  Joachim Knoch,et al.  Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors , 2009 .

[9]  A. Majumdar,et al.  Gate-all-around silicon nanowire MOSFETs and circuits , 2010, 68th Device Research Conference.

[10]  S. Talwar,et al.  Laser-induced lateral epitaxy in fully depleted silicon-on-insulator junctions , 2002 .

[11]  C. Grigoropoulos,et al.  Excimer laser annealing of silicon nanowires , 2007 .

[12]  Nobili,et al.  Precipitation, aggregation, and diffusion in heavily arsenic-doped silicon. , 1994, Physical review. B, Condensed matter.

[13]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[14]  K. Saraswat,et al.  Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope , 2008, 2008 IEEE International Electron Devices Meeting.

[15]  J. Knoch,et al.  Tunneling phenomena in carbon nanotube field‐effect transistors , 2008 .

[16]  James D. Plummer,et al.  Arsenic deactivation enhanced diffusion: A time, temperature, and concentration study , 1998 .

[17]  M. Luisier,et al.  Performance analysis of statistical samples of graphene nanoribbon tunneling transistors with line edge roughness , 2009 .

[18]  H. Riel,et al.  Comparison of VLS grown Si NW tunnel FETs with different gate stacks , 2009, 2009 Proceedings of the European Solid State Device Research Conference.

[19]  Characteristics of heavily doped p+∕n ultrashallow junction prepared by plasma doping and laser annealing , 2005 .

[20]  Arsenic Junction Thermal Stability and High-Dose Boron-Pocket Activation During SPER in nMOS Transistors , 2007, IEEE Electron Device Letters.

[21]  J. Appenzeller,et al.  Band-to-band tunneling in carbon nanotube field-effect transistors. , 2004, Physical review letters.

[22]  F. d’Acapito,et al.  An EXAFS investigation of arsenic shallow implant activation in silicon after laser sub-melt annealing , 2006 .

[23]  N. Young,et al.  Low‐temperature annealing of shallow arsenic‐implanted layers , 1987 .

[24]  S. T. Lee,et al.  Small-Diameter Silicon Nanowire Surfaces , 2003, Science.

[25]  J. Woicik,et al.  Correlation of local structure and electrical activation in arsenic ultrashallow junctions in silicon , 2008 .

[26]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[27]  J. Knoch,et al.  Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices , 2007 .

[28]  H. Riel,et al.  Toward Nanowire Electronics , 2008, IEEE Transactions on Electron Devices.

[29]  W. Riess,et al.  VLS-grown silicon nanowire tunnel FET , 2009, 2009 Device Research Conference.

[30]  Donghyun Kim,et al.  High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: Simulations , 2006, IEEE Transactions on Electron Devices.

[31]  Dmitri E. Nikonov,et al.  Influence of phonon scattering on the performance of p-i-n band-to-band tunneling transistors , 2008 .

[32]  M. Orlowski,et al.  The effect of low-thermal-budget anneals and furnace ramps on the electrical activation of arsenic , 1992 .

[33]  Walter Riess,et al.  Silicon nanowire tunneling field-effect transistors , 2008 .