Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm

With the technology evolution, the decrease of transistors size and, thus, the increase of density of transistors per area, System-on-a-chip (SoC) development is becoming more and more complex. If design, verification, and test are considered, it is noticed how challenging it is getting for designers to plan and manage chips with dozens of billions of transistors, where optimization is a keyword to cope with the IoT world. This paper presents the use of a brand-new tool called ALTRAN to automatically generate the layout of chips using an FDSOI technology.