Fault Coverage Estimation for Non-Random Functional Input Sequences

Statistical stuck-at fault coverage estimation assumes that signals at primary inputs and at other internal gates of the circuit are statistically independent. While valid for random and pseudo-random inputs, this causes substantial errors in coverage estimation for input sequences that are functional and not random, as shown by experimental data presented in this paper. At internal gates, signal correlation due to fanout reconvergence, even for random input sequences, contributes to errors. A significantly improved coverage estimation algorithm is presented in this paper. First, during logic simulation we identify faults that are guaranteed to stay undetected by the applied vectors. Then, after logic simulation, we estimate the detection probabilities of the remaining faults. Compared to Stafan, the statistics gathered during logic simulation are modified in order to eliminate the non-random biasing of the input sequence. Besides the improved detection probabilities, a newly defined effective length (Neff) of the vector sequence corrects for the temporally correlated signals. Experimental results for ISCAS combinational benchmarks demonstrate validity of this approach

[1]  Soumitra Bose,et al.  Upper bounding fault coverage by structural analysis and signal monitoring , 2006, 24th IEEE VLSI Test Symposium.

[2]  Wu-Tung Cheng,et al.  Differential fault simulation for sequential circuits , 1990, J. Electron. Test..

[3]  P. R. Menon,et al.  Critical Path Tracing: An Alternative to Fault Simulation , 1984, IEEE Des. Test.

[4]  Ernst G. Ulrich,et al.  Concurrent simulation of nearly identical digital networks , 1974, Computer.

[5]  Silvano Gai,et al.  Creator: new advanced concepts in concurrent simulation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Sunil Jain,et al.  Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.

[7]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[8]  Dhiraj K. Pradhan,et al.  Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization , 1994, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

[9]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .

[10]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[11]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[12]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Kurt Antreich,et al.  Accelerated Fault Simulation and Fault Grading in Combinational Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  F. Somenzi,et al.  MOZART: a concurrent multilevel simulator , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Dhiraj K. Pradhan,et al.  Accelerated dynamic learning for test pattern generation in combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..