We have designed a CMOS-logic-circuit-compatible DRAM circuit with dual-precharge-level sensing and single-bitline rewriting schemes. This DRAM circuitry is well-matched to modern CMOS logic circuitry; both circuits show similar operating speed dependence on supply voltage and temperature: e.g., they operate down to 0.75 V under V/sub th/ of 0.35 V/spl plusmn/0.1 V with a 0.15-/spl mu/m CMOS technology. Hence, on DRAM containing both types of circuit on a single die: these circuits can reach their maximum performance at the same time over wide-voltage and wide-temperature ranges. The estimated t/sub cycle/ of such as a DRAM is 10 ns at V/sub DD/=1.0 V, V/sub th/=0.35 V, and T/sub j/=75/spl deg/C.