Polymorphic computing paradigms realized for a fpd-based multicomputer

In general, parallel processing has not gained wide acceptance to date, due to many problems associated with cost, design effort, and a limited scope of application. Many of these problems are related to the rigid nature of hardware architecture, which prevents systems from conforming to diverse application needs. The present thesis defines a flexible parallel architecture based on a large number field programmable devices, which enables a wider application scope through architectural flexibility. Several application architectures are presented, demonstrating control flow, data driven, demand driven, and hybrid computing paradigms. A design method for Xilinx 3000 series field programmable logic arrays is presented. This method is hierarchical in construction and enables the rapid prototyping and design of register transfer sequences. Further, a method for expanding designs beyond chip boundaries is also presented. Two neural network applications are discussed and the Kohonen self-organizing feature map is implemented on the present architecture. A network of 588 nodes is executed with network solution times of 2.616ms and 1.368ms per input sample for one and two processors respectively. Field programmable devices can be an invaluable resource to multicomputers and large systems in general. As a result of this study of large system designs, a number of practical and interesting issues related to field programmable devices have been described, including design practices, testing, and architectural flexibility.