A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.

[1]  C. Lerouge,et al.  A fast 16 bit NMOS parallel multiplier , 1984, IEEE Journal of Solid-State Circuits.

[2]  Jun Iwamura,et al.  A high speed and low power CMOS/SOS multiplier-accumulator , 1983 .

[3]  D. B. Rensch,et al.  A fully-scaled NMOS technology for VLSI circuits , 1985 .

[4]  J.Y.-T. Chen,et al.  A novel self-aligned isolation process for VLSI , 1983, IEEE Transactions on Electron Devices.

[5]  H. Shimizu,et al.  A GaAs 16x16 bit parallel multiplier , 1983, IEEE Journal of Solid-State Circuits.

[6]  J. Hui,et al.  Sealed-interface local oxidation technology , 1982, IEEE Transactions on Electron Devices.

[7]  P. Asbeck,et al.  A high-speed LSI GaAs 8x8 bit parallel multiplier , 1982, IEEE Journal of Solid-State Circuits.

[8]  H. Ichino,et al.  An 80ps 2500-gate bipolar macrocell array , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  T. Terada,et al.  A 42ps 2K-gate GaAs gate array , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  K. Suganuma,et al.  A CMOS/SOS multiplier , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  T. Nakashima,et al.  10 ns 8x8 multiplier LSI using super self-aligned process technology , 1983, IEEE Journal of Solid-State Circuits.

[12]  Kuang Yi Chiu,et al.  A bird's beak free local oxidation technology feasible for VLSI circuits fabrication , 1982 .