Miniaturised Sensor Node for Tire Pressure Monitoring (e-CUBES)

[1]  Preben Storås,et al.  Technologies enabling 3D stacking of MEMS , 2010 .

[2]  P. Moor.  3D integration technologies for imaging applications , 2008 .

[3]  H. Reichl,et al.  Development and evaluation of lead free reflow soldering techniques for the flip chip bonding of large GaAs pixel detectors on Si readout chip , 2008, 2008 58th Electronic Components and Technology Conference.

[4]  H. Reichl,et al.  Through silicon via technology — processes and reliability for wafer-level 3D system integration , 2008, 2008 58th Electronic Components and Technology Conference.

[5]  R. Gaddi,et al.  RF–MEMS wafer-level packaging using through-wafer interconnect , 2008 .

[6]  Fan Ji,et al.  Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging , 2008 .

[7]  Nicolas Lietaer.  MEMS Sensor/IC Integration for Miniaturized TPMS (e-CUBES) , 2008 .

[8]  P. Ramm,et al.  3D Process Integration – Requirements and Challenges , 2008 .

[9]  Maaike Margrete Visser Taklo.  3D Integration Technologies for Wireless Sensor Systems (e-CUBES) , 2008 .

[10]  Joshua M. Pearce,et al.  Energy conservation from systematic tire pressure regulation , 2007 .

[11]  E. Ojefors,et al.  Inverted-F Antenna for 3D Integrated Wireless Sensor Applications , 2007, 2007 International workshop on Antenna Technology: Small and Smart Antennas Metamaterials and Applications.

[12]  Anders Rydberg,et al.  Gain and Efficiency Enhanced Flip-Up Antennas for 3D Integrated Wireless Sensor Applications , 2007 .

[13]  Levent Guvenc,et al.  Tire Pressure Monitoring , 2007 .

[14]  Preben Storås,et al.  Development of cost-effective high-density through-wafer interconnects for 3D microsystems , 2006 .

[15]  Jian-Qiang Lu,et al.  Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers , 2006 .

[16]  Mitsumasa Koyanagi,et al.  Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer” , 2006 .

[17]  Chuan Seng Tan,et al.  Silicon Layer Stacking Enabled by Wafer Bonding , 2006 .

[18]  Paul Enquist.  High Density Direct Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications , 2006 .

[19]  Ulrich Ramacher,et al.  3D chip stack technology using through-chip interconnects , 2005, IEEE Design & Test of Computers.

[20]  Keith A. Jenkins,et al.  Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection , 2005, IBM J. Res. Dev..

[21]  P. Ramm,et al.  Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding , 2004 .

[22]  Daniel F. Baldwin,et al.  High density, high aspect ratio through-wafer electrical interconnect vias for MEMS packaging , 2003 .

[23]  Andreas Ostmann,et al.  3D System Integration Technologies , 2003 .

[24]  T. Kenny,et al.  Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates , 2002 .

[25]  K. W. Lee,et al.  A 3-Dimensional Wafer-Level Stacking Technology with Precise Vertical Interconnections to MEMS Applications , 2001 .