Deadlock avoidance for systolic communication
暂无分享,去创建一个
[1] Andrew S. Tanenbaum,et al. Network Protocols , 1981, CSUR.
[2] Philip J. Kuekes,et al. A One Gigaflop VLSI Systolic Processor , 1983, Optics & Photonics.
[3] H. T. Kung. Systolic algorithms for the CMU warp processor , 1984 .
[4] H. T. Kung,et al. Systolic Arrays for (VLSI). , 1978 .
[5] H. T. Kung,et al. The Warp Computer: Architecture, Implementation, and Performance , 1987, IEEE Transactions on Computers.
[6] Charles L. Seitz,et al. The cosmic cube , 1985, CACM.
[7] H. T. Kung. Why systolic architectures? , 1982, Computer.
[8] David E. Foulser,et al. The Saxpy Matrix-1: A General-Purpose Systolic Computer , 1987, Computer.
[9] John G. McWhirter,et al. Some Systolic Array Developments in the United Kingdom , 1987, Computer.
[10] 최종수,et al. Systolic Array Processor Architecture 를 이용한 Discrete Hartley Transform의 병렬처리 실행 ( Parallel Processing Implementation of Discrete Hartley Transform using Systolic Array Processor Architecture ) , 1988 .
[11] J. Blackmer,et al. A 200 Million Operations Per Second (MOPS) Systolic Processor , 1982, Optics & Photonics.
[12] John P. Hayes,et al. Architecture of a Hypercube Supercomputer , 1986, ICPP.
[13] Yasunori Dohi,et al. The architecture of a programmable systolic chip , 1984 .
[14] J. Nash,et al. VLSI Implementation of a linear systolic array , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.
[15] Daniel P. Lopresti,et al. P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences , 1987, Computer.