A high-speed logic LSI using diffusion self-aligned enhancement depletion MOS IC

This paper reports the design, fabrication, and characterization of a diffusion self-aligned enhancement depletion (DSA-ED) MOS IC. It is shown that using DSA structure, a short channel MOST with effective submicron channel length can be realized even by standard photolithographic techniques. High-speed characteristics of a DSA MOST, high gain factors, and small drain junction capacitance are described. The advantage of an ED configuration is discussed. To evaluate the basic performance of the gate, 19-stage ring oscillators with various device sizes have been developed. In the ring oscillator design, the high gain factors of the DSA MOST are fully utilized to minimize the device size and upgrade the performance and packing density. A propagation delay time of 0.65 ns, a power dissipation of 0.15 mW, a power delay product of 0.10 pJ at the supply voltage 2 V, and a packing density of 510 gate/mm/SUP 2/ have been obtained by the single-level metal interconnections of 7 /spl mu/m details. A 4-bit arithmetic logic unit (ALU) has been developed with the same design principle and device size to obtain the 2.9 ns/gate, 0.71 mW/gate performance at the supply voltage of 5 V and 141 gates/mm/SUP 2/ packing density.