Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification

We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP processor.We get a time triggered distributed real-time system by connecting several such ECU's via a common bus. We define a programming model for such a system at the instruction set architecture (ISA) level and prove that it is correctly implemented at the gate level. The proof combines theories of processor correctness, communication systems, program correctness and realistic worst-case execution time (WCET) analysis into a single unified mathematical theory.

[1]  Nancy A. Lynch,et al.  A new fault-tolerant algorithm for clock synchronization , 1984, PODC '84.

[2]  Mark A. Hillebrand,et al.  On the Verification of Memory Management Mechanisms , 2005, CHARME.

[3]  Lee Pike,et al.  Easy Parameterized Verification of Biphase Mark and 8N1 Protocols , 2006, TACAS.

[4]  David A. Patterson,et al.  Computer architecture (2nd ed.): a quantitative approach , 1996 .

[5]  James Wong.  COMPUTER SCIENCE DEPARTMENT , 1971 .

[6]  Wolfgang J. Paul,et al.  Computer architecture - complexity and correctness , 2000 .

[7]  Mark A. Hillebrand,et al.  Dealing with I/O devices in the context of pervasive system verification , 2005, 2005 International Conference on Computer Design.

[8]  Mark A. Hillebrand,et al.  Towards the formal verification of lower system layers in automotive systems , 2005, 2005 International Conference on Computer Design.

[9]  Nancy A. Lynch,et al.  A New Fault-Tolerance Algorithm for Clock Synchronization , 1988, Inf. Comput..

[10]  Iakov Dalinger,et al.  Formal verification of a processor with memory management units , 2013 .

[11]  Daniel Kroening,et al.  Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP , 2003, CHARME.

[12]  Jun Sawada,et al.  Processor Verification with Precise Exeptions and Speculative Execution , 1998, CAV.

[13]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[14]  Christian Jacobi,et al.  Putting it all together – Formal verification of the VAMP , 2006, International Journal on Software Tools for Technology Transfer.

[15]  Julien Schmaltz,et al.  A Formal Model of Lower System Layers , 2006, 2006 Formal Methods in Computer Aided Design.

[16]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .