WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach

Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project1 provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach.

[1]  Reinhold Heckmann,et al.  Worst case execution time prediction by static program analysis , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[2]  Peter Marwedel,et al.  WCET-aware scheduling optimizations for multi-core real-time systems , 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

[3]  François Charot,et al.  GeCoS: A framework for prototyping custom hardware design flows , 2013, 2013 IEEE 13th International Working Conference on Source Code Analysis and Manipulation (SCAM).

[4]  Yun Liang,et al.  Shared cache aware task mapping for WCRT minimization , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[5]  Martin Griebl,et al.  Index Set Splitting , 2000, International Journal of Parallel Programming.

[6]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[7]  Jürgen Becker,et al.  A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling , 2012, 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications.

[8]  Christine Rochange,et al.  Minimizing the cost of synchronisations in the WCET of real-time parallel programs , 2014, SCOPES.

[9]  Marco Caccamo,et al.  A Predictable Execution Model for COTS-Based Embedded Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[10]  William Pugh,et al.  Iteration space slicing and its application to communication optimization , 1997, ICS '97.

[11]  Abhik Roychoudhury,et al.  Static bus schedule aware scratchpad allocation in multiprocessors , 2011, LCTES '11.