NBTI modeling in analog circuits and its application to long-term aging simulations

We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to the negative-bias temperature instability (NBTI). The model is suitable for application in analog circuit design and reproduces the results of existing digital-stress NBTI models in the limit of two-level stress signals. It accounts for recovery effects during intervals of low stress, and it predicts a stress-pattern dependent saturation of the degradation at large operation times. Since the model can be solved numerically in an efficient way, we have direct access to the threshold voltage shift at arbitrary times, in particular to the exact solution at large operation times, without any approximation. We implement the model via the Cadence Spectre URL Finally, we make use of the model to compare the aging properties of several analog stress patterns. We furthermore present the results of an analog circuit-level NBTI simulation of a ring oscillator.

[1]  D. Schmitt-Landsiedel,et al.  Modeling of NBTI-recovery effects in analog CMOS circuits , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[2]  T. Grasser,et al.  Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[3]  A. Kerber,et al.  Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- $k$ Stacks , 2009, IEEE Electron Device Letters.

[4]  Tibor Grasser,et al.  Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities , 2012, Microelectron. Reliab..

[5]  B. Kaczer,et al.  Statistical Model for MOSFET Bias Temperature Instability Component Due to Charge Trapping , 2011, IEEE Transactions on Electron Devices.

[6]  B. Kaczer,et al.  Analytic modeling of the bias temperature instability using capture/emission time maps , 2011, 2011 International Electron Devices Meeting.

[7]  T. Grasser,et al.  On the Distribution of NBTI Time Constants on a Long, Temperature-Accelerated Time Scale , 2013, IEEE Transactions on Electron Devices.

[8]  M. Denais,et al.  NBTI degradation: From physical mechanisms to modelling , 2006, Microelectron. Reliab..

[9]  Mattia Rossetti,et al.  A reversible first-order dispersive model of parametric instability , 2014, Microelectron. Reliab..

[10]  M. Nelhiebel,et al.  Understanding negative bias temperature instability in the context of hole trapping (Invited Paper) , 2009 .

[11]  T. Grasser,et al.  Understanding and modeling AC BTI , 2011, 2011 International Reliability Physics Symposium.

[12]  T. Grasser.  Bias Temperature Instability for Devices and Circuits , 2014 .

[13]  Filippo Alagi,et al.  A study of the interface-trap activation kinetics in the Negative Bias Temperature Instability , 2014, Microelectron. Reliab..

[14]  B. Kaczer,et al.  Physical modeling of NBTI: From individual defects to devices , 2014, 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

[15]  T. Grasser,et al.  The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress , 2010, 2010 IEEE International Reliability Physics Symposium.

[16]  Bernard P. Zeigler,et al.  Theory of modeling and simulation , 1976 .