Design Guidelines for FPGA Based Design

Over the past decade FPGAs are primarily used for SOC based design and for ASIC prototyping. The architecture of modern FPGA is complex and consists of up to few mega logic cells or logic blocks. An FPGA consists of finite number of resources and it is essential for a designer to implement the design by estimating the logic requirement that is the resource or device utilization. Modern FPGA architecture consists of sea of array of Logic blocks or logic cells, Block RAMs, Hard and soft IP cores, embedded multiplier, DSP blocks, Processor cores and other glue logic. Modern FPGAs are used as prototyping device for SOC based design and development. The major design constraints are area, speed and power. By using proper design and coding practices the large or medium FPGAs can be used for SOC prototyping. The coding and design guidelines are used to improve the design performance by optimizing design for glitch free behavior. Good design practices always aid in successful design migration between FPGA and ASIC for both prototyping and production. The paper presents most of the efficient coding and design guidelines by using Verilog HDL for FPGA based designs. Keywords—FPGA, Verilog, ASIC, HDL, Logic Block, STA, FSM, SOC, Lint, CDC, PLL, DLL, IP, LUT, IOB, ,mux, SDF,DSP.