Advances on Low Power Designs for SRAM Cell

As the development of complex metal oxide semiconductor (CMOS) technology, fast low-power static random access memory (SRAM) has become an important component of many very large scale integration (VLSI) chips. Lot of applications preferred to use the 6T SRAM because of its robustness and very high speed. However, the leakage current has increasing with the increase SRAM size. It consumes more power while in standby condition. The power dissipation has become an importance consideration due to the increase integration, operating speeds and the explosive growth of battery operated appliances. The objective of this paper is to review and discuss several methods to overcome the power dissipation problem of SRAM. Low power SRAM can be produced with improvement in term of power dissipation during the standby condition, write operation and read operation. Discharging and charging of bit lines consumes more power during write ‘0’ and ‘1’compared to read operation. One of the methods to produce low power SRAM design is with make modification circuit at a standard 6T SRAM cell. This modification circuit will help to decrease power dissipation and leakage current. Several method was discussed in this paper for understand the method to produce low power design of SRAM cell. Recommendations for future research are also set out. This review gives some idea for future research to improve the design of low power SRAM cell.

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