Methodology for switching characterization evaluation of wide band-gap devices in a phase-leg configuration
暂无分享,去创建一个
Leon M. Tolbert | Fred Wang | Puqi Ning | Zhenxian Liang | Zheyu Zhang | Ben Guo | Benjamin J. Blalock | L. Tolbert | Fred Wang | P. Ning | Ben Guo | B. Blalock | Zheyu Zhang | Zhenxian Liang
[1] Jan Abraham Ferreira,et al. Integration of high frequency current shunts in power electronic circuits , 1992 .
[2] J. Roudet,et al. MOSFET switching behaviour under influence of PCB stray inductance , 1996, IAS '96. Conference Record of the 1996 IEEE Industry Applications Conference Thirty-First IAS Annual Meeting.
[3] J.L. Schanen,et al. Switching disturbance due to source inductance for a power MOSFET: analysis and solutions , 1996, PESC Record. 27th Annual IEEE Power Electronics Specialists Conference.
[4] P. Venkataraghavan,et al. The dV/dt capability of MOS-gated thyristors , 1998 .
[5] J. Lai,et al. Characterization of power electronics system interconnect parasitics using time domain reflectometry , 1998, PESC 98 Record. 29th Annual IEEE Power Electronics Specialists Conference (Cat. No.98CH36196).
[6] Thomas Wu. CDV/DT INDUCED TURN-ON IN SYNCHRONOUS BUCK REGULATORS , 2001 .
[7] Joseph Brandon Witcher,et al. Methodology for Switching Characterization of Power Devices and Modules , 2003 .
[8] H. Shah,et al. Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics , 2004, Nineteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2004. APEC '04..
[9] S. Mazumder,et al. DV/DT related spurious gate turn-on of bidirectional switches in a high-frequency cycloconverter , 2005, IEEE Transactions on Power Electronics.
[10] G. Stojcic,et al. Characterization of $Cdv/dt$ Induced Power Loss in Synchronous Buck DC–DC Converters , 2007 .
[11] Zheng Chen. Characterization and Modeling of High-Switching-Speed Behavior of SiC Active Devices , 2009 .
[12] R. Burgos,et al. Design considerations of a fast 0-Ω gate-drive circuit for 1.2 kV SiC JFET devices in phase-leg configuration , 2009, 2009 IEEE Energy Conversion Congress and Exposition.
[13] Dushan Boroyevich,et al. Experimental parametric study of the parasitic inductance influence on MOSFET switching characteristics , 2010, The 2010 International Power Electronics Conference - ECCE ASIA -.
[14] Weifeng Sun,et al. Analysis and design optimization of brushless DC motor's driving circuit considering the Cdv/dt induced effect , 2010, 2010 IEEE Energy Conversion Congress and Exposition.
[15] D. Boroyevich,et al. Evaluation of the switching characteristics of a gallium-nitride transistor , 2011, 2011 IEEE Energy Conversion Congress and Exposition.
[16] I. Josifovic,et al. Improving SiC JFET Switching Behavior Under Influence of Circuit Parasitics , 2012, IEEE Transactions on Power Electronics.
[17] Weimin Zhang,et al. Analysis of the switching speed limitation of wide band-gap devices in a phase-leg configuration , 2012, 2012 IEEE Energy Conversion Congress and Exposition (ECCE).
[18] Design Considerations for Designing with Cree SiC Modules Part 2 . Techniques for Minimizing Parasitic Inductance , 2013 .
[19] Weimin Zhang,et al. Evaluation of 600 V cascode GaN HEMT in device characterization and all-GaN-based LLC resonant converter , 2013, 2013 IEEE Energy Conversion Congress and Exposition.
[20] J. Strydom,et al. Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter , 2013, 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC).