A systematic system level design methodology for dual band CMOS RF receivers

A systematic system-level design methodology for dual-band RF CMOS receiver is proposed. The methodology helps the designer to find the optimum set of specifications of the receiver's building blocks for minimizing the power consumption. Our analysis is based on analytical expressions for the input referred noise, input referred third order intercept point and gain as a function of the frequency for the various blocks. This methodology is applied to a dual-band receiver for the GSM (900 MHz) and PCS (1900 MHz) standards. Simulations show that having an LNA with a constant gain behavior reduces the power consumption by 75% compared to an LNA with a decreasing gain versus frequency.

[1]  B. Razavi,et al.  A 900 MHz/1.8 GHz CMOS receiver for dual band applications , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[2]  A. Bevilacqua,et al.  An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  Theerachet Soorapanth,et al.  RF Linearity of Short-Channel MOSFETs , 1997 .

[4]  Edgar Sánchez-Sinencio,et al.  CMOS RF receiver system design: a systematic approach , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[6]  K. Halonen,et al.  A dual-band RF front-end for WCDMA and GSM applications , 2001 .

[7]  A.A. Abidi,et al.  Noise in RF-CMOS mixers: a simple physical model , 2000, IEEE Journal of Solid-State Circuits.

[8]  Yeon-Jae Jung,et al.  A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan , 2005 .