Novel TFET circuits for high-performance energy-efficient heterogeneous MOSFET/TFET logic

TFET's steep subthreshold slope and asymmetric I<inf>DS</inf>-V<inf>DS</inf> characteristics enable energy-efficiency and novel circuits that are not possible with MOSFETs. Logic with low-V<inf>DD</inf> and memory with low-V<inf>MIN</inf> are required and possible with TFET. To increase performance despite low-V<inf>DD</inf>, circuits and logic are re-designed for TFET's unique I–V characteristics. Asymmetric I<inf>DS</inf>-V<inf>DS</inf> improves circuit design. Efficiency gains from transistor steep-slope enable heterogeneous MOSFET-TFET logic re-design for higher clock rate and greater parallelization.