Design of application-specific 3D Networks-on-Chip architectures

The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging systems-on-chip (SoC) design paradigms based on networks-on-chip (NoC) interconnection architectures to 3D chip designs. In this paper, we consider the problem of designing application-specific 3D-NoC architectures that are optimized for a given application. We present novel 3D-NoC synthesis algorithms that make use of accurate power and delay models for 3D wiring with through-silicon vias. In particular, we present a very efficient 3D-NoC synthesis algorithm called ripup-reroute-and-router-merging (RRRM), that is based on a rip-up and reroute formulation for routing flows and a router merging procedure for network optimization. Experimental results on 3D-NoC design cases show that our synthesis results can on average achieve a 74% reduction in power consumption and a 17% reduction in hop count over regular 3D mesh implementations and a 52% reduction in power consumption and a 17% reduction in hop count over optimized 3D mesh implementations.

[1]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[2]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Mahmut T. Kandemir,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[4]  Jason Cong,et al.  Thermal-driven multilevel routing for 3-D ICs , 2005, Asia and South Pacific Design Automation Conference.

[5]  Natalie D. Enright Jerger,et al.  Circuit-Switched Coherence , 2007, IEEE Computer Architecture Letters.

[6]  Hideharu Amano,et al.  Tightly-Coupled Multi-Layer Topologies for 3-D NoCs , 2007, 2007 International Conference on Parallel Processing (ICPP 2007).

[7]  Bill Lin,et al.  Custom Networks-on-Chip Architectures With Multicast Routing , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Charles Addo-Quaye,et al.  Thermal-aware mapping and placement for 3-D NoC designs , 2005, Proceedings 2005 IEEE International SOC Conference.

[9]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, MICRO.

[10]  Josep Torrellas,et al.  An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors , 1996, Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing.

[11]  K. Soejima,et al.  A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.

[12]  Krishnan Srinivasan,et al.  Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms , 2007, 2007 Asia and South Pacific Design Automation Conference.

[13]  H. Shirota,et al.  A new rip-up and reroute algorithm for very large scale gate arrays , 1996, Proceedings of Custom Integrated Circuits Conference.

[14]  S. K. Kim,et al.  Three-dimensional integration: technology, use, and issues for mixed-signal applications , 2003 .

[15]  William A. Dees,et al.  Automated Rip-Up and Reroute Techniques , 1982, 19th Design Automation Conference.

[16]  Krisztián Flautner,et al.  PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor , 2006, ASPLOS XII.

[17]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[18]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[19]  Jaehyuk Huh,et al.  Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture , 2003, ISCA '03.

[20]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[21]  Bill Lin,et al.  Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees , 2008, 2008 Asia and South Pacific Design Automation Conference.

[22]  Manfred Glesner,et al.  Multicast Parallel Pipeline Router Architecture for Network-on-Chip , 2008, 2008 Design, Automation and Test in Europe.

[23]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[24]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[25]  Guoqing Chen,et al.  Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[27]  Ling Zhang,et al.  Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[28]  K. W. Lee,et al.  Three-dimensional shared memory fabricated using wafer stacking technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[29]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[30]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[31]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Jeong-Gun Lee,et al.  Implications of Rent's Rule for NoC Design and Its Fault-Tolerance , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[33]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[34]  Alberto L. Sangiovanni-Vincentelli,et al.  A Detailed Router Based on Incremental Routing Modifications: Mighty , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  Jan M. Van Campenhout,et al.  Generating synthetic benchmark circuits for evaluating CAD tools , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Fernando Gehm Moraes,et al.  Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[37]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[38]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[39]  Axel Jantsch,et al.  Connection-oriented multicasting in wormhole-switched networks on chip , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[40]  Sachin Sapatnekar,et al.  Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach , 2003, ICCAD 2003.

[41]  Xiaola Lin,et al.  Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers , 1994, IEEE Trans. Parallel Distributed Syst..

[42]  Sung Kyu Lim,et al.  Thermal-aware steiner routing for 3D stacked ICs , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[43]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[44]  Chita R. Das,et al.  A novel dimensionally-decomposed router for on-chip communication in 3D architectures , 2007, ISCA '07.