RF Potential of a 0 . 18-m CMOS Logic Device Technology

The radio-frequency (rf) performance of a 0.18m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies( and max) the minimum noise figure ( min) and associated power gain( ) and the 1/ -noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the rf performance without any technology process modifications. Changing to N2O gate dielectrics is shown to greatly reduce the 1/ noise without sacrificing the ac performance. The power amplifier characteristics of CMOS at low power levels are also discussed.

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