Datapath scheduling with multiple supply voltages and level converters

We present an algorithm called MOVER (Multiple Operating Voltage Energy Reduction) to minimize datapath energy dissipation through use of multiple supply voltages. In a single voltage design, the critical path length, clock period, and number of control steps limit minimization of voltage and power. Multiple supply voltages permit localized voltage reductions to take up remaining schedule slack. MOVER initially finds one minimum voltage for an entire datapath. It then determines a second voltage for operations where there is still schedule slack. New voltages con be introduced and minimized until no schedule slack remains. MOVER was exercised for a variety of DSP datapath examples. Energy savings ranged from 0% to 50% when comparing dual to single voltage results. The benefit of going from two to three voltages never exceeded 15%. Power supply costs are not reflected in these savings, but a simple analysis shows that energy savings can be achieved even with relatively inefficient DC-DC converters. Datapath resource requirements were found to vary greatly with respect to number of supplies. Area penalties ranged from 0% to 170%. Implications of multiple voltage design for IC layout and power supply requirements are discussed.

[1]  Mark C. Johnson,et al.  Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[2]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[3]  Massoud Pedram,et al.  Energy Minimization Using Multiple Supply Voltages , 1997, ISLPED.

[4]  Niraj K. Jha,et al.  An iterative improvement algorithm for low power data path synthesis , 1995, ICCAD.

[5]  Alex Orailoglu,et al.  Microarchitectural synthesis of performance-constrained, low-power VLSI designs , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[6]  Majid Sarrafzadeh,et al.  Variable voltage scheduling , 1995, ISLPED '95.

[7]  Mohamed I. Elmasry,et al.  A global optimization approach for architectural synthesis , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  Kimiyoshi Usami,et al.  Clustered voltage scaling technique for low power , 1995 .

[9]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[10]  Catherine H. Gebotys,et al.  Optimal VLSI Architectural Synthesis , 1992 .

[11]  Catherine H. Gebotys,et al.  Optimal VLSI Architectural Synthesis: Area, Performance and Testability , 1991 .

[12]  S. Katkoori,et al.  Profile-driven behavioral synthesis for low-power VLSI systems , 1995, IEEE Design & Test of Computers.

[13]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Anantha P. Chandrakasan,et al.  Design of portable systems , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[15]  Massoud Pedram,et al.  Energy Minimization Using Multiple Supply Voltages , 1997 .

[16]  John P. Knight,et al.  Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level , 1995, 32nd Design Automation Conference.

[17]  Catherine H. Gebotys,et al.  An optimal methodology for synthesis of DSP multichip architectures , 1995, J. VLSI Signal Process..

[18]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[19]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[20]  Niraj K. Jha,et al.  An iterative improvement algorithm for low power data path synthesis , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[21]  Robert W. Brodersen,et al.  High-efficiency low-voltage dc-dc conversion for portable applications , 1994 .

[22]  J. E. Mitchell,et al.  Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[23]  Mark C. Johnson,et al.  Optimal Selection of Supply Voltages and Level Conversions During Low Power Data Path Scheduling , 1996 .