Reusing Test Access Mechanisms

Starting from this chapter, we propose several solutions to develop low-cost interconnection fabrics (See Fig. 2.1), which are essential for ensuring debug capability. Our first work is to address one of the main difficulties in post-silicon validation. That is the limited debug access bandwidth to internal signals. Based on the observation that SoC devices often contain dedicated bus-based test access mechanisms (TAMs) that are used to transfer test data between external testers and embedded cores, in this chapter, we propose to reuse these precious TAM resources for real-time debug data transfer in post-silicon validation. This strategy significantly increases debug bandwidth with negligible routing overhead. To support different TAM architectures and debug scenarios, DfD structures are introduced at both core test wrapper level and system level. Simulation results demonstrate the effectiveness of the proposed approach at low DfD cost.