Low power BIST design by hypergraph partitioning: methodology and architectures

Power consumption of digital systems may increase significantly during testing. In this paper, we propose a novel low power/energy Built-in Self Test (BIST) strategy based on circuit partitioning. The strategy consists of partitioning the original circuit into structural subcircuits so that each subcircuit can be successively tested through different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. The average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the subcircuits is not so far from the test length for the original circuit. The proposed strategy can be applied to either test-per-scan or test-per-clock BIST schemes by slightly modifying conventional TPG structures as illustrated in this paper. Results on ISCAS circuits show that average power reduction of up to 62%, peak power reduction of up to 57%, and energy reduction of up to 82% can be achieved at a very low area cost in terms of area overhead and with almost no penalty on the circuit timing.

[1]  S.,et al.  An Efficient Heuristic Procedure for Partitioning Graphs , 2022 .

[2]  Kaushik Roy,et al.  POWERTEST: a tool for energy conscious weighted random pattern testing , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[3]  Vishwani D. Agrawal,et al.  Power constraint scheduling of tests , 1994, Proceedings of 7th International Conference on VLSI Design.

[4]  Sandeep K. Gupta,et al.  LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  S.K. Gupta,et al.  A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[6]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[7]  Sandeep K. Gupta,et al.  DS-LFSR: a new BIST TPG for low heat dissipation , 1997, Proceedings International Test Conference 1997.

[8]  João Paulo Teixeira,et al.  Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[9]  Nur A. Touba,et al.  Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[10]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.

[11]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[12]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning , 1995 .

[14]  Brian W. Kernighan,et al.  A proper model for the partitioning of electrical circuits , 1972, DAC '72.

[15]  Christian Landrault,et al.  Low power BIST by filtering non-detecting vectors , 1999, ETW.

[16]  Patrick Girard,et al.  Circuit partitioning for low power BIST design with minimized peak power consumption , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

[17]  S. Kumar,et al.  Power Dissipation During Testing: Should We Worry About it? , 1997, VTS.

[18]  Patrick Girard,et al.  A test vector inhibiting technique for low energy BIST design , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[19]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[20]  Jason Cong,et al.  A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design , 1993, 30th ACM/IEEE Design Automation Conference.

[21]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[22]  Patrick Girard,et al.  On using machine learning for logic BIST , 1997, Proceedings International Test Conference 1997.

[23]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[24]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.