A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range

A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage (VDD) droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency (FCLK) adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce FCLK in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect VDD droops across a wide range of operating conditions. The auto-calibration circuit maximizes the VDD-droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% VDD droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively.