Analysis of multithreaded microprocessors under multiprogramming

We examine multithreading to improve uniprocessor cost/performance on multiple processes. Processor utilization and cache behavior are studied analytically and under simulation by interleaving reference traces to model timesharing and multithreading. Multithreading a small number of threads is superior with large on-chip caches and significant memory latency. The switch need not be extremely fast. Surprisingly, miss ratios under multithreading may be lower than under timesharing, because switch-on-miss multithreading favors processes with better cache behavior.

[1]  Anoop Gupta,et al.  The directory-based cache coherence protocol for the DASH multiprocessor , 1990, ISCA '90.

[2]  A. Gupta,et al.  Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results , 1989, ISCA '89.

[3]  David E. Culler,et al.  Analysis of multithreaded architectures for parallel computing , 1990, SPAA '90.

[4]  David E. Culler,et al.  Dataflow architectures , 1986 .

[5]  Burton J. Smith,et al.  A processor architecture for Horizon , 1988, Proceedings. SUPERCOMPUTING '88.

[6]  Robert H. Halstead,et al.  MASA: a multithreaded processor architecture for parallel symbolic computing , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[7]  Anant Agarwal,et al.  APRIL: a processor architecture for multiprocessing , 1990, ISCA '90.

[8]  David A. Patterson,et al.  Evaluation of a 'stall' cache: an efficient restricted onchip instruction cache , 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.