Memory device with quadratic index structure and operation method thereof

The invention discloses a memory device with quadratic index structure. The device comprises a multi-queue memory cell, an index table module and two index registers, wherein the multi-queue memory cell is logically divided into N first in first out queues (FIFO), is provided with independent read port and write port and can simultaneously perform read and write operation on any FIFO in the cell; the index table module is used for storing the index information of the N FIFO queues; the index information of each FIFO queue is stored in one row of the index table module; and the two index registers are used for temporarily storing the index information read from the index table module for read operation and write operation to simultaneously use.