On test time reduction using pattern overlapping, broadcasting and on-chip decompression
暂无分享,去创建一个
[1] Jan Schmidt,et al. Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.
[2] Shianling Wu,et al. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG , 2008, IEEE Design & Test of Computers.
[3] Bashir M. Al-Hashimi,et al. Variable-length input Huffman coding for system-on-a-chip test , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Lei Li,et al. Test data compression using dictionaries with fixed-length indices [SOC testing] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..
[5] Ondrej Novak,et al. Scan chain configuration method for broadcast decompressor architecture , 2011, 2011 12th Latin American Test Workshop (LATW).
[6] Rohit Kapur,et al. Changing the scan enable during shift , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..
[7] Tracy Larrabee,et al. Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Nur A. Touba,et al. Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[9] Kuen-Jong Lee,et al. Broadcasting test patterns to multiple circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Gary S. Ditlow,et al. Random Pattern Testability , 1984, IEEE Transactions on Computers.
[11] Ahmad A. Al-Yamani,et al. Seed encoding with LFSRs and cellular automata , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[12] Nilanjan Mukherjee,et al. Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[14] Sybille Hellebrand,et al. Data compression for multiple scan chains using dictionaries with corrections , 2004 .
[15] Nur A. Touba,et al. Adjustable Width Linear Combinational Scan Vector Decompression , 2003, ICCAD.
[16] Krishnendu Chakrabarty,et al. Frequency-Directed Run-Length (FDR) Codes , 2002 .
[17] Jiri Jenícek,et al. Test Pattern Compression Based on Pattern Overlapping , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.
[18] Hans-Joachim Wunderlich,et al. RESPIN++ - deterministic embedded test , 2002, Proceedings The Seventh IEEE European Test Workshop.
[19] Rohit Kapur,et al. Minimizing the Impact of Scan Compression , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[20] Ondrej Novák,et al. COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits , 2005, EDCC.
[21] Janak H. Patel,et al. Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).
[22] Bernard Courtois,et al. Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .
[23] Wilfried Daehn,et al. Hardware Test Pattern Generation for Built-In Testing , 1981, International Test Conference.
[24] Ondrej Novak,et al. Test pattern compression based on pattern overlapping and broadcasting , 2011, 2011 10th International Workshop on Electronics, Control, Measurement and Signals.
[25] Krishnendu Chakrabarty,et al. Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[26] Jiri Jenícek,et al. Advanced scan chain configuration method for broadcast decompressor architecture , 2011, 2011 9th East-West Design & Test Symposium (EWDTS).
[27] Kewal K. Saluja,et al. Built-in self-testing of random-access memories , 1990, Computer.
[28] Kuen-Jong Lee,et al. Using a single input to support multiple scan chains , 1998, ICCAD '98.