M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors

Recent study shows that a further speedup can be achieved by RISC-based extensible processors if the incorporated custom functional units (CFUs) can execute functions with more than two inputs and one output. However, mechanisms to execute multiple-input, multiple-output (MIMO) custom functions in a RISC processor have not been addressed. This paper proposes an extension for single-issue RISC processors based on a CFU that can execute custom functions with up to six inputs and three outputs. To minimize the change to the core processor, we maintain the operand bandwidth of two inputs, one output per cycle and transfer the extra operands and results using repeated custom instructions. While keeping such an limit sacrifices some speedup, our experiments show that the MIMO extension can still achieve an average 51% increase in speedup compared to a dual-input, single-output (DISO) extension and an average 27% increase in speedup compared to a multiple-input, single-output (MISO) extension.

[1]  Jan Hoogerbrugge,et al.  ConCISe: a compiler-driven CPLD-based instruction set accelerator , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[2]  Stamatis Vassiliadis,et al.  The MOLEN processor prototype , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[3]  Tulika Mitra,et al.  Characterizing embedded applications for instruction-set extensible processors , 2004, Proceedings. 41st Design Automation Conference, 2004..

[4]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[5]  Tulika Mitra,et al.  Scalable custom instructions identification for instruction-set extensible processors , 2004, CASES '04.

[6]  Paolo Ienne,et al.  On the Limits of Processor Specialisation by Mapping Dataflow Sections on Ad-hoc Functional Units , 2001 .

[7]  Jason Cong,et al.  Instruction set extension with shadow registers for configurable processors , 2005, FPGA '05.

[8]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[9]  Nikil D. Dutt,et al.  ISEGEN: generation of high-quality instruction set extensions by iterative improvement , 2005, Design, Automation and Test in Europe.

[10]  Frank Vahid,et al.  A quantitative analysis of the speedup factors of FPGAs over processors , 2004, FPGA '04.

[11]  Gerry Kane,et al.  MIPS RISC Architecture , 1987 .