A Low Power Implementation Strategy for SOC
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Xu Huang | Yingtai Li | Luncai Liu | Xin Lei | Yiru Fu
[1] CapabilityyFarid N. NajmECE. Towards a High-Level Power Estimation , 1996 .
[2] Robert C. Aitken,et al. Low Power Methodology Manual - for System-on-Chip Design , 2007 .
[3] Zhang Jinyi,et al. A System-level Mixed DFT-TAM Structure For SoC Design , 2005, 2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis.
[4] K. Itoh. A Historical Review of Low-Power, Low-Voltage Digital MOS Circuits Development , 2013, IEEE Solid-State Circuits Magazine.
[5] S. Chen,et al. Deep sub-micron ultra-low power CMOS device design and optimization , 2004, The Fourth International Workshop on Junction Technology, 2004. IWJT '04..
[6] Frank Emnett,et al. Power Reduction Through RTL Clock Gating , 2001 .