Optimal conditions for Boolean and current detection of floating gate faults

This paper studies the Boolean (Static Voltage) and the I/sub ddq/ (Static Current) detection of Floating Gate faults due to large opens on transistor gate connections. We show that existing electrical models describing the behavior of FGT faults fail to allow the prediction of the floating gate potential due to the unpredictable parameters such as the initial changes and the polysilicon-to-bulk capacitance. We propose the twin-transistor structure as a basis for a general analysis of the Boolean and I/sub ddq/ detection of FGT faults. Using this analysis, optimal conditions for detection are defined for Boolean as well as I/sub ddq/ tests.

[1]  Michel Renovell,et al.  Electrical analysis and modeling of floating-gate fault , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  M. Renovell,et al.  Topology dependence of floating gate faults in MOS integrated circuits , 1986 .

[3]  Charles F. Hawkins,et al.  THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[4]  Michel Renovell,et al.  Test strategy sensitivity to defect parameters , 1997, Proceedings International Test Conference 1997.

[5]  Simon Johnson,et al.  Residual charge on the faulty floating gate CMOS transistor , 1994, Proceedings., International Test Conference.

[6]  F. Joel Ferguson,et al.  An unexpected factor in testing for CMOS opens: the die surface , 1996, Proceedings of 14th VLSI Test Symposium.

[7]  Joan Figueras,et al.  IDDQ testing of single floating gate defects using a two-pattern vector , 1996 .

[8]  Víctor H. Champac,et al.  Testability of floating gate defects in sequential circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[9]  Jochen A. G. Jess,et al.  Probability analysis for CMOS floating gate faults , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[10]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[11]  Antonio Rubio,et al.  Logic testability of defective floating gate CMOS latches , 1992 .

[12]  Antonio Rubio,et al.  Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  R. Keith Treece,et al.  CMOS IC stuck-open-fault electrical effects and design considerations , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[14]  Antonio Rubio,et al.  Analysis of the floating gate defect in CMOS , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[15]  Michel Renovell,et al.  Testing for floating gates defects in CMOS circuits , 1998 .