A comparison of the decision tree approach and the neural-networks-based heuristic dynamic programming approach for subcircuit extraction problem

The applications of non-standard logic device are increasing fast in the industry. Many of these applications require high speed, low power, functionality and flexibility, which cannot be obtained by standard logic device. These special logic cells can be constructed by the topology design strategy automatically or manually. However, the need arises for the topology design verification. The layout versus schematic (LVS) analysis is an essential part of topology design verification, and subcircuit extraction is one of the operations in the LVS testing. In this paper, we first provided an efficient decision tree approach to the graph isomorphism problem, and then effectively applied it to the subcircuit extraction problem based on the solution to the graph isomorphism problem. To evaluate its performance, we compare it with the neural networks based heuristic dynamic programming algorithm (SubHDP) which is by far one of the fastest algorithms for subcircuit extraction problem.