Minimizing Syntactic Variance with Assignment Decision Diagrams

Author(s): Chaiyakul, Viraphol; Gajski, Daniel D.; Ramachandran, Loganath | Abstract: Most synthesis systems generate designs from hardware descriptions by relating each language construct to a particular hardware structure. Thus, designs obtained from these systems are dependent on description styles. In other words, semantically equivalent descriptions with different ordering or grouping of conditional and assignment statements, could generate designs with distinctively diff erent cost and performance. This paper introduces a new representation that minimizes the syntactic variance of different description styles. We also propose an algorithm for conversion of hardware descriptions into this new representation. In addition, using this representation for scheduling results in a drastic reduction on the number of control steps required to synthesize the description. Experimental data on severa[ examples show effectiveness ofthe proposed approach.

[1]  Ajoy K. Bose,et al.  Bridge: a versatile behavioral synthesis system , 1988, DAC '88.

[2]  Kazutoshi Wakabayashi,et al.  A resource sharing and control synthesis method for conditional branches , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  Daniel Gajski,et al.  Flow Graph Representation , 1986, 23rd ACM/IEEE Design Automation Conference.

[4]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[5]  S. J. McFarland,et al.  The value trace : a data base for automated digital design , 1978 .

[6]  R. Composano,et al.  Path-based scheduling for synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[7]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[8]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[9]  C. Y. Lee.  Representation of switching circuits by binary-decision programs , 1959 .

[10]  Daniel D. Gajski,et al.  Synthesis from VHDL , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[11]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Robert A. Walker,et al.  A Survey of high-level synthesis systems , 1991 .

[13]  Donald E. Thomas,et al.  Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Taewhan Kim,et al.  A scheduling algorithm for conditional resource sharing , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.