Synthesis for manufacturability: a sanity check

As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synthesis stage and has been shown capable of reducing manufacturing cost up to 10%. As in other cases, raising the abstraction layer where optimization is applied is expected to yield substantial gains. This paper focuses on a new approach to design for manufacturability: logic synthesis for manufacturability. This methodology consists of replacing the traditional area-driven technology mapping with a new manufacturability-driven one. We leverage existing logic synthesis tools to test our method. The results obtained by using STMicroelectronics 0.13 /spl mu/m library confirm that this approach is a promising solution for designing circuits with lower manufacturing cost, while retaining performance. Finally, we show that our synthesis for manufacturability can achieve even larger cost reduction when yield-optimized cells are added to the library, thus enabling a wider area-yield tradeoff exploration.

[1]  Tughrul Arslan,et al.  Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Jitendra Khare,et al.  Manufacturability and testability oriented synthesis , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[3]  J. Khare,et al.  Manufacturability analysis of standard cell libraries , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[4]  Jitendra Khare,et al.  Maximizing wafer productivity through layout optimizations , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[5]  Wojciech Maly,et al.  Design for manufacturability in submicron domain , 1996, Proceedings of International Conference on Computer Aided Design.

[6]  Israel Koren,et al.  Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.

[7]  Duncan M. Walker.  Yield simulation for integrated circuits , 1987 .

[8]  I. Koren,et al.  Layout-synthesis techniques for yield enhancement , 1995 .

[9]  Wojciech Maly,et al.  Performance-manufacturability tradeoffs in IC design , 1998, Proceedings Design, Automation and Test in Europe.

[10]  I. Koren,et al.  Yield enhancement vs. performance improvement in VLSI circuits , 1995, Proceedings of International Symposium on Semiconductor Manufacturing.

[11]  Wojciech Maly,et al.  Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs , 1996, Proceedings of International Conference on Computer Aided Design.