Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection

Globalization trends in integrated circuit (IC) design using deep submicron (DSM) technologies are leading to increased vulnerability of IC against malicious intrusions. These malicious intrusions are referred to hardware Trojans. One way to address this threat is to utilize unique electrical signatures of ICs, and any deviation from this signature helps in detecting the potential attack paths. Recently we proposed hybrid macro synchronous micro asynchronous (MSMA) pipeline technique while utilizing, non-conventional, asynchronous circuits to generate timing signature. However, traditionally generating these timing signatures with environmental uncertainties require extensive simulations. It is known to the engineering community that computer simulations have its limitations due to the associated heavy computational requirements. In this paper, as a more accurate alternative, we propose a framework to detect the vulnerable paths in the MSMA pipeline for hardware Trojan detection using formal verification methods. In particular, the paper presents a formal model of the MSMA pipeline and its verification results for both functional and timing properties.

[1]  Michael S. Hsiao,et al.  A region based approach for the identification of hardware Trojans , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[2]  Michael S. Hsiao,et al.  A Novel Sustained Vector Technique for the Detection of Hardware Trojans , 2009, 2009 22nd International Conference on VLSI Design.

[3]  Mark Mohammad Tehranipoor,et al.  Trustworthy Hardware: Identifying and Classifying Hardware Trojans , 2010, Computer.

[4]  Mark Mohammad Tehranipoor,et al.  A study on the effectiveness of Trojan detection techniques using a red team blue team approach , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[5]  Mark Mohammad Tehranipoor,et al.  Case study: Detecting hardware Trojans in third-party digital IP cores , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

[6]  Alberto Griggio,et al.  The MathSAT 5 SMT Solver ⋆ , 2012 .

[7]  Giorgio Di Natale,et al.  Is Side-Channel Analysis really reliable for detecting Hardware Trojans? , 2012 .

[8]  S. R. Hasan,et al.  Modified null convention logic pipeline to detect soft errors in both null and data phases , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

[9]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[10]  Osman Hasan,et al.  Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[11]  Marco Roveri,et al.  The nuXmv Symbolic Model Checker , 2014, CAV.

[12]  Farinaz Koushanfar,et al.  A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection , 2011, IEEE Transactions on Information Forensics and Security.

[13]  Prabhat Mishra,et al.  Pre-silicon security verification and validation: A formal perspective , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[14]  Osman Hasan,et al.  Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

[15]  Yier Jin Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[16]  Florian Schupfer,et al.  Hardware Trojan detection by specifying malicious circuit properties , 2013, 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication.