Numerical Function Generators Using LUT Cascades

This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA)

[1]  Jack E. Volder The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[2]  Michael J. Schulte,et al.  Approximating Elementary Functions with Symmetric Bipartite Tables , 1999, IEEE Trans. Computers.

[3]  David H. Douglas,et al.  ALGORITHMS FOR THE REDUCTION OF THE NUMBER OF POINTS REQUIRED TO REPRESENT A DIGITIZED LINE OR ITS CARICATURE , 1973 .

[4]  Tsutomu Sasao,et al.  Realization of multiple-output functions by reconfigurable cascades , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[5]  Earl E. Swartzlander,et al.  Hardware Designs for Exactly Rounded Elemantary Functions , 1994, IEEE Trans. Computers.

[6]  Tsutomu Sasao Design Methods for Multiple-Valued Input Address Generators , 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

[7]  Wayne Luk,et al.  A Gaussian noise generator for hardware-based simulations , 2004, IEEE Transactions on Computers.

[8]  Takashi Horiyama,et al.  Minimization of fractional wordlength on fixed-point conversion for high-level synthesis , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[9]  Shinobu Nagayama,et al.  On the optimization of heterogeneous MDDs , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Michael J. Schulte,et al.  Symmetric bipartite tables for accurate function approximation , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[11]  David M. Lewis Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit , 1994, IEEE Trans. Computers.

[12]  Antonio Cantoni,et al.  Optimal Curve Fitting With Piecewise Linear Functions , 1971, IEEE Transactions on Computers.

[13]  Wayne Luk,et al.  Hierarchical segmentation schemes for function evaluation , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[14]  Munehiro Matsuura,et al.  A method to decompose multiple-output logic functions , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Shinobu Nagayama,et al.  Compact representations of logic functions using heterogeneous MDDs , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

[16]  Tsutomu Sasao,et al.  Application of LUT cascades to numerical function generators , 2004 .

[17]  Jean-Michel Muller,et al.  "Partially rounded" small-order approximations for accurate, hardware-oriented, table-based methods , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[18]  Masahiro Fujita,et al.  Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping , 1993, 30th ACM/IEEE Design Automation Conference.

[19]  Ray Andraka,et al.  A survey of CORDIC algorithms for FPGA based computers , 1998, FPGA '98.

[20]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[21]  Arnaud Tisserand,et al.  Multipartite table methods , 2005, IEEE Transactions on Computers.

[22]  Shinobu Nagayama,et al.  Programmable numerical function generators based on quadratic approximation: architecture and synthesis method , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[23]  Michael J. Schulte,et al.  The Symmetric Table Addition Method for Accurate Function Approximation , 1999, J. VLSI Signal Process..

[24]  Weng-Fai Wong,et al.  Fast Evaluation of the Elementary Functions in Single Precision , 1995, IEEE Trans. Computers.

[25]  Shinobu Nagayama,et al.  Programmable numerical function generators: architectures and synthesis method , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[26]  Jie Cheng,et al.  High-performance architectures for elementary function generation , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[27]  Wayne Luk,et al.  Non-uniform Segmentation for Hardware Function Evaluation , 2003, FPL.

[28]  Vijay K. Jain,et al.  High-speed double precision computation of nonlinear functions , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[29]  Naofumi Takagi,et al.  Function evaluation by table look-up and addition , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[30]  Lei Lin,et al.  A universal nonlinear component and its application to WSI , 1993 .

[31]  Shuzo Yajima,et al.  Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation , 1991, IEEE Trans. Computers.

[32]  Darrall Henderson Elementary Functions: Algorithms and Implementation , 2000 .

[33]  Wayne Luk,et al.  Optimizing hardware function evaluation , 2005, IEEE Transactions on Computers.