A timing error detection latch using subthreshold source-coupled logic

Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At Vdd=300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

[1]  Massimo Alioto,et al.  Analysis and design of ultra-low power subthreshold MCML gates , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[2]  Anantha Chandrakasan,et al.  Sub-threshold Design for Ultra Low-Power Systems , 2006, Series on Integrated Circuits and Systems.

[3]  K.A. Bowman,et al.  Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[4]  Christofer Toumazou,et al.  Nanopower Subthreshold MCML in Submicrometer CMOS Technology , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Yusuf Leblebici,et al.  Leakage Current Reduction Using Subthreshold Source-Coupled Logic , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  David Blaauw,et al.  Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Yusuf Leblebici,et al.  Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems , 2009, 2009 Proceedings of ESSCIRC.

[8]  David Blaauw,et al.  A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation , 2011, IEEE Journal of Solid-State Circuits.

[9]  David M. Bull,et al.  RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[10]  Matthew J. Turnquist,et al.  Measurement of a timing error detection latch capable of sub-threshold operation , 2009, 2009 NORCHIP.

[11]  Matthew J. Turnquist,et al.  Subthreshold timing error detection performance analysis , 2010, 2010 12th Biennial Baltic Electronics Conference.

[12]  A. Tajalli,et al.  Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications , 2008, IEEE Journal of Solid-State Circuits.

[13]  David Blaauw,et al.  A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[14]  M. Turnquist,et al.  Sub-threshold operation of a timing error detection latch , 2009, 2009 Ph.D. Research in Microelectronics and Electronics.