On correlating structural tests with functional tests for speed binning of high performance design

The use of functional vectors has been an industry standard for speed binning purposes of high performance ICs. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural testing an effective alternative to functional testing for speed binning, structural patterns need to correlate with functional test frequencies closely. We investigate the correlation between functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/spl trade/ instruction set architecture.

[1]  M. Abadir,et al.  Design-for-test methodology for Motorola PowerPC/sup TM/ microprocessors , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  W. Robert Daasch,et al.  Obtaining high defect coverage for frequency-dependent defects in complex ASICs , 2003, IEEE Design & Test of Computers.

[3]  Subhasish Mitra,et al.  Delay defect characteristics and testing strategies , 2003, IEEE Design & Test of Computers.

[4]  Dawit Belete,et al.  Use of DFT techniques in speed grading a 1 GHz+ microprocessor , 2002, Proceedings. International Test Conference.

[5]  Nandu Tendolkar,et al.  Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[6]  Alfred L. Crouch,et al.  AC scan path selection for physical debugging , 2003, IEEE Design & Test of Computers.

[7]  Carol Pyron,et al.  Next generation PowerPC/sup TM/ microprocessor test strategy improvements , 1997, Proceedings International Test Conference 1997.

[8]  Nandu Tendolkar,et al.  At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[9]  Rohit Kapur,et al.  Speed binning with path delay test in 150-nm technology , 2003, IEEE Design & Test of Computers.

[10]  Janusz Rajski,et al.  High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.

[11]  Dawit Belete,et al.  DFT advances in Motorola's Next-Generation 74xx PowerPC/sup TM/ microprocessor , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).