A New ATPG Technique (ExpoTan) for Testing Analog Circuits

In analog testing, usage of a single sinusoid as a test signal when compared to multitone signal, and fault detection with digital counting technique, facilitate the test implementation with simple built-in self-test hardware and make testing more cost effective. In this paper, a novel test-set-selection technique known as ExpoTan for testing linear-time-invariant (LTI) circuits is presented. The authors formulate the test generation problem with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. For identification of a test signal the ExpoTan technique combines test generation and test-set-compaction tasks in a single phase and generates an efficient compacted test set. The experimental results show that the testing of LTI circuits using ExpoTan technique for the benchmark circuits achieves the required fault coverage with shorter testing time and test generation time

[1]  Ian O'Connor,et al.  Extremely Low-Power Logic , 2004, DATE '04.

[2]  Luca Benini,et al.  A survey of design techniques for system-level dynamic power management , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[3]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[4]  Kaushik Roy,et al.  Dynamic VTH Scaling Scheme for Active Leakage Power Reduction , 2002, DATE.

[5]  Lalit M. Patnaik,et al.  A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Sule Ozev,et al.  Automated test development and test time reduction for RF subsystems , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[7]  Chenming Hu,et al.  Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology] , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[8]  Jacob A. Abraham,et al.  Analog Testing with Time Response Parameters , 1996, IEEE Des. Test Comput..

[9]  Prashant Goteti,et al.  Test set selection for structural faults in analog IC's , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Abhijit Chatterjee,et al.  Partial simulation-driven ATPG for detection and diagnosis of faults in analog circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[11]  Dragan Maksimovic,et al.  Switching regulator with dynamically adjustable supply voltage for low power VLSI , 2001, IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.37243).

[12]  David Blaauw,et al.  Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment , 2004, Proceedings. 41st Design Automation Conference, 2004..

[13]  José Luis Huertas,et al.  Analog and mixed-signal benchmark circuits-first release , 1997, Proceedings International Test Conference 1997.

[14]  John E. Dennis,et al.  Numerical methods for unconstrained optimization and nonlinear equations , 1983, Prentice Hall series in computational mathematics.

[15]  Kurt Antreich,et al.  Analog testing by characteristic observation inference , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  B. Kaminska,et al.  Fault observability analysis of analog circuits in frequency domain , 1996 .

[17]  Kaushik Roy Leakage power reduction in low-voltage CMOS designs , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[18]  Abhijit Chatterjee,et al.  Prediction of analog performance parameters using fast transienttesting , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Zhen Guo,et al.  Test limitations of parametric faults in analog circuits , 2003, IEEE Trans. Instrum. Meas..

[20]  Anantha Chandrakasan,et al.  Optimal supply and threshold scaling for subthreshold CMOS circuits , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[21]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[22]  Seongwon Kim,et al.  Efficient test set design for analog and mixed-signal circuits and systems , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

[23]  Resve A. Saleh,et al.  Power-delay metrics revisited for 90 nm CMOS technology , 2005, Sixth international symposium on quality electronic design (isqed'05).

[24]  T. Sakurai,et al.  V/sub TH/-hopping scheme for 82% power saving in low-voltage processors , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[25]  Gang Qu,et al.  Energy reduction techniques for multimedia applications with tolerance to deadline misses , 2003, DAC.

[26]  Seongwon Kim,et al.  Hierarchical ATPG for Analog Circuits and Systems , 2001, IEEE Des. Test Comput..

[27]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[28]  Trevor Mudge,et al.  Dynamic voltage scaling on a low-power microprocessor , 2001 .

[29]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[30]  M. Soma Automatic test generation algorithms for analogue circuits : Mixed signal & analogue IC test technology , 1996 .

[31]  Parimal Pal Chaudhuri,et al.  Test solution for OTA based analog circuits , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.